This relates to integrated circuits and, more particularly, to performing incremental register retiming of an integrated circuit design.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which have led to performance increases.
To further increase the performance, solutions such as register retiming have been proposed, where registers are moved among portions of combinational logic, thereby achieving a more balanced distribution of delays between registers and thus potentially a higher clock frequency at which the integrated circuit may be operated.
Register retiming is often performed when delays between registers are well known. For example, register retiming may be performed after physical design operations such as placement and routing have been performed on the integrated circuit design.
Occasionally, the integrated circuit design may change, for example as the result of a change in the specification or as the result of an error that was located late in the design cycle. Such changes to the integrated circuit design may require a full iteration through the physical design operations and the register retiming operation.
It is within this context that the embodiments herein arise.